LCOL=Val_0x0, TJT=Val_0x0, EXCOL=Val_0x0, NCARR=Val_0x0, RWT=Val_0x0, EXDEF=Val_0x0, LCARR=Val_0x0
Receive Transmit Status Register
| TJT | Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled) and JD bit is reset in the ETH_MAC_CONFIGURATION register. This bit is set when the packet size exceeds 16,383 bytes and the JD bit is set in the ETH_MAC_CONFIGURATION register. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): No transmit jabber timeout 1 (Val_0x1): Transmit jabber timeout occurred |
| NCARR | No Carrier When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set, this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): Carrier is present 1 (Val_0x1): No carrier |
| LCARR | Loss of Carrier When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set, this bit indicates that the loss of carrier occurred during packet transmission, that is, the ETH_CRS_DV signal was inactive for one or more transmission clock periods during packet transmission. This bit is valid only for packets transmitted without collision. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): Carrier is present 1 (Val_0x1): Loss of carrier |
| EXDEF | Excessive Deferral When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set and the DC bit is set in the ETH_MAC_CONFIGURATION register, this bit indicates that the transmission ended because of excessive deferral of over 24,288-bit times (155,680 when Jumbo packet is enabled). Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): No excessive deferral 1 (Val_0x1): Excessive deferral |
| LCOL | Late Collision When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set, this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including preamble). This bit is not valid if the Underflow error occurs. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): No collision 1 (Val_0x1): Late collision is sensed |
| EXCOL | Excessive Collisions When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set, this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the ETH_MAC_CONFIGURATION register, this bit is set after the first collision and the packet transmission is aborted. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): No collision 1 (Val_0x1): Excessive collision is sensed |
| RWT | Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the ETH_MAC_CONFIGURATION[WD] bit is reset. This bit is also set when a packet with length greater than 16,383 bytes is received and the ETH_MAC_CONFIGURATION[WD] bit is set. Access restriction applies. Clears on read (or write of 1 when the ETH_MAC_CSR_SW_CTRL[RCWE] bit is set). Self-set to 1 on internal event. 0 (Val_0x0): No receive watchdog timeout 1 (Val_0x1): Receive watchdog timed out |